[[1] OWAIDAT, M. Q.-HIJJAWI, R. S.-M QHALIFEH, J. M. Interstitial Single Resistor in a Network of Resistors Application of the Lattice Green’Vs Function : J. Phys. A: Math. Theor. 43, 375204.]Search in Google Scholar
[[2] WU, F. Y. : Theory of Resistor Networks: the Two-Point Resistance, J. Phys. A: Mathematical and General 37 (2004), 6653-73.]Search in Google Scholar
[[3] KILBY, J. S. : Turning Potential into Realities: The Invention of the Integrated Circuit (Nobel lecture), ChemPhysChem 2 (2001), 482-489.10.1002/1439-7641(20010917)2:8/9<482::AID-CPHC482>3.0.CO;2-Y]Search in Google Scholar
[[4] VLACH, J.-SINGHAL, K. : Computer Methods for Circuits Analysis and Design, Van Nostrand Reinhold press, 1994.]Search in Google Scholar
[[5] BRENKUˇ S, J.-STOPJAKOV´A, V.-GYEPES, G. Numerical Method for dc Fault Analysis Simplification and Simulation Time Reduction : in: Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013. Proceedings of the 16th IEEE International Symposium on, 2013, pp. 170-174.10.1109/DDECS.2013.6549811]Search in Google Scholar
[[6] TSIATOUHAS, Y.-MOISIADIS, Y.-HANIOTAKIS, T.-NIKOLOS, D.-ARAPOYANNI, A. : A New Technique for {IDDQ}, Testing in Nanometer Technologies, Integration, the {VLSI}, Journal 31 No. 2 (2002), 183-194.]Search in Google Scholar
[[7] BERESINSKI, M.-BOREJKO, T.-PLESKACZ,W.-STOPJAKOVA, V. : Built-in Current Monitor for iddq Testing in cmos 90 nm technology, in: Design and Diagnostics of Electronic Circuits and Systems, DDECS 2008, 11th IEEE Workshop on, 2008, pp. 1-4.10.1109/DDECS.2008.4538797]Search in Google Scholar
[[8] CERŇANOVÁ, V. On an Explicit Solution of a Finite Network Problem: in: ODAM 2013.]Search in Google Scholar