Accès libre

Design and Implementation of Low Power and High Data Rate Edge Coded Signaling Architecture for IoT Devices

M Jamuna

M Jamuna

Department of ECE, Bangalore Institute of TechnologyIndia
Recherchez cet auteur sur
Sciendo|Google Scholar
Jamuna, M
 et 
A. M VijayaPrakash

A. M VijayaPrakash

Department of ECE, Bangalore Institute of TechnologyIndia
Recherchez cet auteur sur
Sciendo|Google Scholar
VijayaPrakash, A. M
  
28 sept. 2024
Design and Implementation of Low Power and High Data Rate Edge Coded Signaling Architecture for IoT Devices's Cover Image
À propos de cet article
Article précédent
Article suivant
Citez
Télécharger la couverture
Catégorie d'article: Research Article
Publié en ligne: 28 sept. 2024
Reçu: 19 mai 2024
DOI: https://doi.org/10.2478/ijssis-2024-0029
Mots clés
© 2024 M Jamuna et al., published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Figure 1:

Architecture of a CDR circuit using PLL. CDR, clock and data recovery; PLL, phase-locked loop.
Architecture of a CDR circuit using PLL. CDR, clock and data recovery; PLL, phase-locked loop.

Figure 2:

(A) Normal serial transfer; (B) Edge-coded transmitter; (C) Edge-coded.
(A) Normal serial transfer; (B) Edge-coded transmitter; (C) Edge-coded.

Figure 3:

ECS packet formation. ECS, edge coded signaling.
ECS packet formation. ECS, edge coded signaling.

Figure 4:

Example: ECS packet formation. ECS, edge coded signaling.
Example: ECS packet formation. ECS, edge coded signaling.

Figure 5:

Standard ECS transmission (Data = 267). ECS, edge coded signaling.
Standard ECS transmission (Data = 267). ECS, edge coded signaling.

Figure 6:

(A) Standard ECS transmission (Data = 267) (B) DDR-ECS transmission = (Data = 267) (C) DDR-ECS transmission (Data = 132). DDR, double data rate; ECS, edge coded signaling.
(A) Standard ECS transmission (Data = 267) (B) DDR-ECS transmission = (Data = 267) (C) DDR-ECS transmission (Data = 132). DDR, double data rate; ECS, edge coded signaling.

Figure 7:

Proposed DDR-ECS architecture. DDR, double data rate; ECS, edge coded signaling.
Proposed DDR-ECS architecture. DDR, double data rate; ECS, edge coded signaling.

Figure 8:

Segmentation/bit splitter.
Segmentation/bit splitter.

Figure 9:

Simulation result showing data segmentation for input 3EC8.
Simulation result showing data segmentation for input 3EC8.

Figure 10:

Segment encoder.
Segment encoder.

Figure 11:

Simulation results showing Index codes and NOIs.
Simulation results showing Index codes and NOIs.

Figure 12:

Index code generation.
Index code generation.

Figure 13:

Simulation result showing encoded data.
Simulation result showing encoded data.

Figure 14:

Simulation result showing Index one output.
Simulation result showing Index one output.

Figure 15:

Simulation result showing Index two output.
Simulation result showing Index two output.

Figure 16:

Simulation result showing Flag bit.
Simulation result showing Flag bit.

Figure 17:

Proposed DDR-ECS packet. DDR, double data rate; ECS, edge coded signaling.
Proposed DDR-ECS packet. DDR, double data rate; ECS, edge coded signaling.

Figure 18:

FSM implementation of proposed DDR-ECS transmitter. DDR, double data rate; ECS, edge coded signaling.
FSM implementation of proposed DDR-ECS transmitter. DDR, double data rate; ECS, edge coded signaling.

Figure 19:

Simulation result showing subsequent iterations.
Simulation result showing subsequent iterations.

Figure 20:

Toggle counter.
Toggle counter.

Figure 21:

Example of DDR-ECS pulse generation using toggle counter. DDR, double data rate; ECS, edge coded signaling.
Example of DDR-ECS pulse generation using toggle counter. DDR, double data rate; ECS, edge coded signaling.

Figure 22:

Simulation result showing generation of transmission pulse for the input 3EC8.
Simulation result showing generation of transmission pulse for the input 3EC8.

Figure 23:

Positive edge detector.
Positive edge detector.

Figure 24:

Positive edge detection.
Positive edge detection.

Figure 25:

Negative edge detector.
Negative edge detector.

Figure 26:

Negative edge detection.
Negative edge detection.

Figure 27:

Counter enable generation.
Counter enable generation.

Figure 28:

Rising and falling edge of a pulse.
Rising and falling edge of a pulse.

Figure 29:

Simulation result of counter 1.
Simulation result of counter 1.

Figure 30:

Simulation result of counter 2.
Simulation result of counter 2.

Figure 31:

Simulation result of memory unit.
Simulation result of memory unit.

Figure 32:

Simulation result of data decoder.
Simulation result of data decoder.

Figure 33:

Simulation output of 16-bit DDR ECS transmitter module with data input 4539.Double data rate ECS.
Simulation output of 16-bit DDR ECS transmitter module with data input 4539.Double data rate ECS.

Figure 34:

Simulation output of 16-bit DDR ECS receiver module with data input 4539. Double data rate ECS.
Simulation output of 16-bit DDR ECS receiver module with data input 4539. Double data rate ECS.

Comparison of IoT communication protocols

Wired protocols Wireless protocol
Characteristics 1-wire protocol PIC protocol PDC protocol Dynamic ECS protocol Bluetooth Zigbee Z-wave 6 LoWPAN SigFox
Standard NA NA NA NA IEEE 802.15.1 [20] IEEE 802.15.4 [20] Z-Wave [20] IEEE 802.15.4 [20] Sigfox [21]
Frequency bands NA 24 MHz [16] 25 MHz [17] 25 MHz [18] 2.4 GHz [22] 2.4 GHz [23] 868–908 MHz [24] 868 MHz (EU) 868 MHz (EU)
915 MHz (USA) 902 MHz (USA)
2.4 GHz (Global) [24]
Network 1-wire network [8] Ultra-low power network [16] Ultra-low power network [17] Ultra-low power network [18] WPAN [25] WPAN [25] WPAN [25] WPAN [25] LPWAN [26]
Topology Master and Slave [8] Master and Slave [16] Master and Slave [17] Master and Slave [18] Star–Bus [27] Star, Mesh cluster Mesh Star-Mesh [27] Star
Power Low power protocol 26.6 μW [16] 25 μW [17] 19 μW [18] 30 mA Low power [28] 30 mA Low power [28] 2.5 mA Low power [29] (1–2 years lifetime on batteries) [29] 10–100 mW
Data rate 16 Kbps [16] 4.1 Mbps [16] 7.33 Mbps [17] 4.2–26.7 (6.4 Avg.) [18] 1 Mbps 250 Kbps 40 Kbps [30] 250 Kbps 100–600 bps
Common applications IoT sensor applications [16] IoT sensor applications [16] IoT sensor applications [17] IoT sensor applications [18] Wireless headsets, audio applications [31] Controlling and monitoring home industry [31] Home monitoring and controlling [31] Monitor and control through the internet [31] Energy meters & street lighting

Index coding

Possible data after encoding No. of pulses (existing) [8, 9] Number of 1’s Index code No. of pulses (proposed)
0001 1 1 001 1
0010 2 1 010 2
0100 3 1 011 3
1000 4 1 100 4
0011 3 2 001 1
0101 4 2 010 2
0110 5 2 011 3
1001 5 2 100 4
1010 6 2 101 5
1100 7 2 110 6

Encoded data and number of 1’s

Regular data Encoding/inversion Number of 1’s Flag
0000 0000 0 0
0001 0001 1 0
0010 0010 1 0
0011 0011 2 0
0100 0100 1 0
0101 0101 2 0
0110 0110 2 0
0111 1000 1 1
1000 1000 1 0
1001 1001 2 0
1010 1010 2 0
1011 0100 1 1
1100 1100 2 0
1101 0010 1 1
1110 0001 1 1
1111 0000 0 1

DDR-ECS transceiver synthesis results using 65 nm technology

Name of the module Power (µW) Area (µm2) Data rate (Mb/s)
Proposed 16 bit DDR-ECS ≈13 1,755 12–73.5
DDR-ECS [10] ≈19 1,943 7.8–44.4
ECS [9] ≈19 ≈2,098 4.2–26.7
PDC [4] ≈25 ≈2,150 4.8–12.9
PIC [3] ≈26.6 ≈2,356 3.1–8.5
Langue:
Anglais
Périodicité:
1 fois par an
Sujets de la revue:
Ingénierie, Présentations et aperçus, Ingénierie, autres
RSS Feed de la revue