Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique With Pseudo NMOS and Transmission Gate Logics
, , , , et | 01 sept. 2017
Publié en ligne: 01 sept. 2017
Pages: 344 - 357
Reçu: 27 mai 2017
Accepté: 15 juin 2017
© 2017 T.R. Dinesh Kumar et al., published by Sciendo
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