The designed circuit features a dual-stage Low Noise Amplifier (LNA) in which, a common source (CS) configuration is employed to achieve high gain, while the subsequent stage adopts a Complementary Common Gate (CCG) setup provide the low power consumption. This arrangement ensures that both transistors share the same biasing current, promoting energy efficiency. The two stages are interconnected in a cascade configuration, amplifying the overall gain and concurrently mitigating noise. To facilitate wideband matching in the input stage, a parallel RC feedback mechanism is implemented. Additionally, a pair of mutually coupled inductors in the CS and CCG stages contribute to rendering the input impedance exclusively resistive, concurrently minimizing the overall size of the circuit. All simulations were done using 65 nm CMOS technology in Cadence Virtuoso. The proposed LNA showcases a Noise Figure (NF) of 3.2 dB, a Peak Power Gain (