<abstract xmlns="http://www.w3.org/1999/xhtml"><p>This paper presents FPGA and softcore CPU based solution for large datasets parallel core calculation using rough set methods. Architectures shown in this paper have been tested on two real datasets running presented solutions inside FPGA unit. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.</p></abstract>

This paper presents FPGA and softcore CPU based solution for large datasets parallel core calculation using rough set methods. Architectures shown in this paper have been tested on two real datasets running presented solutions inside FPGA unit. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.

Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets

Journal of Artificial Intelligence and Soft Computing Research

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

This paper presents FPGA and softcore CPU based solution for large datasets parallel core calculation using rough set methods. Architectures shown in this...

Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets

Publicado en línea: 29 ene 2021

Páginas: 99 - 110

Recibido: 05 may 2020

Aceptado: 05 nov 2020

DOI: https://doi.org/10.2478/jaiscr-2021-0007

Palabras clave
rough sets, FPGA, core attributes, parallel architecture

© 2021 Maciej Kopczyński et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets

Publicado en línea: 29 ene 2021

Páginas: 99 - 110

Recibido: 05 may 2020

Aceptado: 05 nov 2020

DOI: https://doi.org/10.2478/jaiscr-2021-0007

Palabras claverough sets, FPGA, core attributes, parallel architecture

© 2021 Maciej Kopczyński et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Palabras clave
rough sets, FPGA, core attributes, parallel architecture