A Methodology for the Optimization Of Multi-program Shared Scratchpad Memory

[1]G. E. Moore. “No exponential is forever: but “Forever” can be delayed!”, IEEE Intl. SolidState Circuit Conf., Lisbon, Portugal, February 12-15, 2003, pp. 20-23.

[2]C.M. Kirsch and R. Wilhelm. “Grand challenges in embedded software”, 7th ACM&IEEE Intl. Conf. on Embedded software, Salzburg, Austria, September 30 - October 03, 2007, pp. 2-6.10.1145/1289927.1289930

[3]ITRS. “International Techbology Roadmap for Semiconductors”, 2009, http://www.public.itrs.net.

[4]W.A. Wulf and S.A. Mckee. “Hitting the Memory Wall: Implications of the Obvious”, ACM Computer Archtiecture News, Vol. 23, Issue 1, March, 1995, pp. 24-29.10.1145/216585.216588

[5]W.R. Fujita and K. Yanagisawa. “Low-power and high-speed advantages of DRAM-logic integration for multimedia systems”, IECE Transactions on Electron, Vol. 80, Issue 12, December, 1997, pp. 1523–1531.

[6]J. Hennessy and D. Patterson. Computer Architecture A Quantitative Approach, Palo Alto, CA: Morgan Kaufmann, 3 edition, 2002.

[7]P.R. Panda, N.D. Dutt. and A. Nicolau. “Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications”, 1997 European conference on Design and Test, Paris, France, March 17-20, 1997, pp. 7-11.

[8]S. Steinke, L. Wehmeyer, B. Lee and P. Marwedel. “Assigning Program and Data Objects to Scratchpad for Energy Reduction”, IEEE Conf. on Design, automation and test in Europe, Paris, France, March 4-8, 2002, pp. 409-415.

[9]M. Verma, S. Steinke and P. Marwedel. “Data partitioning for maximal scratchpad usage”, 2003 conference on Asia South Pacific design automation, Kasuga, Japan, January 21-24, 2003, pp. 77-83.10.1145/1119772.1119788

[10]S. Anantharaman and P.R. Panda. “An Efficient Data Partitioning Method for Limited Memory Embedded Systems”, ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, Montreal, Canada, June 19–20, 1998, pp. 108-122.10.1007/BFb0057792

[11]O. Avissar, R. Barua and D. Stewart. “An optimal memory allocation scheme for scratchpad-based embedded systems”, IEEE Trans. on Embedded Computing Sys. Vol. 1, Issue 1, November, 2003, pp. 6-26.10.1145/581888.581891

[12]K.D. Cooper and T.H. Harvey. “Compiler-controlled memory”, eighth international conference on Architectural support for programming languages and operating systems, San Jose, California, United States, October 02 - 07, 1998, pp. 2-11.10.1145/291069.291010

[13]M. Kandemir and A. Choudhary. “Compiler-directed scratch pad memory hierarchy design and management”, 39th conference on Design automation, New Orleans, Louisiana, USA, June 10 - 14, 2002, pp. 628-633.10.1145/513918.514077

[14]O. Ozturk, M. Kandemir and I. Kolcu. “Shared scratch-pad memory space management”, 7th International Symposium on Quality Electronic Design, San Jose, CA, March 27-29, 2006, pp. 576-584.

[15]A. Ramachandran and M.F. Jacome. “Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, Issue 6, June, 2005, pp. 832-848.10.1109/TCAD.2005.844081

[16]A. Ramachandran and M.F. Jacome. “Energy-delay efficient data memory subsystems: suitable for embedded media ‘processing’“, IEEE Signal Processing Magazine, Vol. 22, Issue 3, May, 2005, pp. 23-37.10.1109/MSP.2005.1425895

[17]F. Angiolini, L. Benini and A. Caprara. “Polynomial-time algorithm for on-chip scratchpad memory partitioning”, 2003 international conference on Compilers, architecture and synthesis for embedded systems, San Jose, California, USA, October 30 - November 01, 2003, pp. 318-326.10.1145/951710.951751

[18]F. Angiolini, L. Benini and A. Caprara. “An efficient profile-based algorithm for scratchpad memory partitioning”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, Vol. 24, Issue 11, November, 2005, pp. 1660-1676.10.1109/TCAD.2005.852299

[19]P.R. Panda, N.D. Dutt and A. Nicolau. “Data memory organization and optimizations in application-specific systems”, IEEE Design & Test of Computers, Vol. 18, Issue 3, May, 2001, pp. 56-68.10.1109/54.922803

[20]M. Kandemir and I. Kadayif. “Compiler-directed selection of dynamic memory layouts”, ninth international symposium on Hardware/software codesign, Copenhagen, Denmark, April 25-27, 2001, pp. 219-224.10.1145/371636.371733

[21]E. Brockmeyer, M. Miranda, H. Corporaal and F. Catthoor. “Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations”, IEEE Conf. on Design, Automation and Test in Europe, Munich, Germany, March 3-7, 2003, pp.1070-1075.

[22]B. Egger, J. Lee and H. Shin. . “Scratchpad memory management for portable systems with a memory management unit”, 6th ACM & IEEE Intl. Conf. on Embedded software, Seoul, Korea, October 22-25, 2006, pp. 321-330.10.1145/1176887.1176933

[23]O. Ozturk, M. Kandemir and I. Demirkiran. “Data compression for improving SPM behavior”, 41st annual conference on Design automation, San Diego, California, USA, June 07-11, 2004, pp. 401-410.10.1145/996566.996680

[24]A.R. Ravindran, P.D. Nagarkar and G.S. Dasika. “Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache”, ACM Intl. Symp. on Code generation and optimization, San Jose, California, March 20 - 23, 2005, pp. 179-190.

[25]I. Issenin, E. Brockmeyer, M. Miranda and N.D. Dutt. “Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies”, IEEE Conf. on Design, automation and test in Europe, Vol. 1, Paris, France, February 16 - 20, 2004, pp. 202-207.

[26]M. Ruggiero, A. Guerri and D. Bertozzi. “Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip”, IEEE Conf. on Design, automation and test in Europe, Munich, Germany, March 06 - 10, 2006, pp. 3-8.10.1109/DATE.2006.243950

[27]B. Scholz, B. Burgstaller and J.L. Xue. “Minimizing bank selection instructions for partitioned memory architecture”, 2006 international conference on Compilers, architecture and synthesis for embedded systems, Seoul, Korea, October 22 - 25, 2006, pp. 201-211.10.1145/1176760.1176786

[28]S. Udayakumaran and R. Barua. “Compiler-decided dynamic memory allocation for scratchpad based embedded systems”, 2003 Intl. Conf. on Compilers, architecture and synthesis for embedded systems, San Jose, California, USA, October 30 - November 01, 2003, pp. 276286.10.1145/951710.951747

[29]S. Udayakumaran, A. Dominguez and R. Barua. “Dynamic allocation for scratch-pad memory using compile-time decisions”, ACM Trans. on Embedded Computing Sys., Vol. 5, Issue 2, May, 2006, pp. 472-511.10.1145/1151074.1151085

[30]S. Udayakumaran and R. Barua. “An integrated scratch-pad allocator for affine and non-affine code”, IEEE Conf. on Design, automation and test in Europe, Munich, Germany, March 06 - 10, 2006, pp. 925-930.10.1109/DATE.2006.243809

[31]P.R. Panda, N.D. Dutt And A. Nicolau. “Data memory organization and optimizations in application-specific systems”, IEEE Design & Test of Computers, Vol 18, Issue 3, May, 2001, pp. 56-68.10.1109/54.922803

[32]M. Kandemir, J. Irwin, G. Chen and I. Kolcu. “Banked scratch-pad memory management for reducing leakage energy consumption”, 2004 IEEE/ACM International conference on Computer-aided design, San Jose, California, USA, November 07 - 11, 2004, pp. 120-124.

[33]Intel Corporation, Intel XScale® PXA27x Processor Family, http://www.intel.com/design/pca/probref/253820.htm.

[34]W. Hu, T.Z. Chen, B. Xie and Q.S. Shi. “Embedded Real-Time Linux on Chip: Next Generation Operation System for Embedded System”, 8th Real-Time Linux Workshop, Lanzhou China, October 12-15, 2006, pp. 167-172.

[35]C. Lee, M. Potkonjak and W.H. Manione-Smith. “Mediabench: A tool for evaluating multimedia and communications systems”, 30th Annu. IEEE Conf. Microarchitecture, Research Triangle Park, North Carolina, United States, December 01 - 03, 1997, pp. 330– 335.

[36]M.R. Guthaus. “Mibench: A free, commercially representative embedded benchmark suite”, IEEE Annual Workshop on Workload Characterization, Austin, TX, USA, December 2, 2001, pp. 3-14.