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A study on the design of D flip-flop with set and reset using GDI scheme

Seungmin Jung

Seungmin Jung

Division of Software Convergence, Hanshin UniversityOsan-si, South Korea
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Jung, Seungmin
  
18. Juli 2025
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Artikel-Kategorie: Research Article
Online veröffentlicht: 18. Juli 2025
Eingereicht: 06. Mai 2025
DOI: https://doi.org/10.2478/ijssis-2025-0036
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© 2025 Seungmin Jung, published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Figure 1:

Basic GDI cell and its function. GDI, gate diffusion input.
Basic GDI cell and its function. GDI, gate diffusion input.

Figure 2:

Functional block diagram of fingerprint sensor chip. (A) AND (B) OR (C) MUX.
Functional block diagram of fingerprint sensor chip. (A) AND (B) OR (C) MUX.

Figure 3:

Hybrid GDI technique. GDI, gate diffusion input.
Hybrid GDI technique. GDI, gate diffusion input.

Figure 4:

Conventional CMOS set/reset D flip-flop (DFFSR_C).
Conventional CMOS set/reset D flip-flop (DFFSR_C).

Figure 5:

Proposed GDI set/reset D flip-flop (DFFSR_G). CK, DFFSR_G, GDI, gate diffusion input.
Proposed GDI set/reset D flip-flop (DFFSR_G). CK, DFFSR_G, GDI, gate diffusion input.

Figure 6:

Functional simulation result of DFFSR_G.
Functional simulation result of DFFSR_G.

Figure 7:

Verilog-HDL based RTL code for synthesis and P&R verification using DFFSR_G. P&R, placement and routing.
Verilog-HDL based RTL code for synthesis and P&R verification using DFFSR_G. P&R, placement and routing.

Figure 8:

Configuration condition for openROAD.
Configuration condition for openROAD.

Figure 9:

SDC condition for openROAD.
SDC condition for openROAD.

Figure 10:

Layout result of 64 bit counter using DFFSR_G.
Layout result of 64 bit counter using DFFSR_G.

Functions of GDI technique_

Input
 Output Function
G P N
A B ‘1’ A + B OR
A ‘0’ B A·B AND
A B C A¯B+AC {\rm{\bar A}}{\rm{B}}+{\rm{AC}} MUX
A ‘1’ ‘0’ A¯ {\rm{\bar A}} NOT

Truth table of DFFSR operation_

RN SN D CK Q[n+1] QN[n+1]
0 0 X X 0 1
1 0 X X 1 0
0 0 X X 1 0
1 1 0 ↑ 0 1
1 1 1 ↑ 1 0
1 1 X ↓ Q[n] QN[n]

Summary of 64 bit counter P&R_

DFFSR_C DFFSR_G
Number of I/O ports 131
Number of nets 390
Number of cells 196
Combinational area (µm2) 4301.0 4301.0
Noncombinational area (µm2) 5535.1 4317.4
Total cell area (µm2) 9836.2 8618.4

Summary of DFFSR performance comparison_

Number of MOS TR. clk_q_tplh (sec) clk_q_tphl (sec) average (sec) power_avg (uW/MHz)
DFFSR_C 42 3.60E-10 3.17E-10 3.39E-10 0.211
DFFSR_G 28 5.97E-10 6.04E-10 6.00E-10 0.205
Improvement 33% –77% 3%
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