AMD (2023b). VC709 Evaluation Board for the Virtex-7 FPGA, AMD, San Jose, https://www.xilinx.com/support/documentation/boards_and_kits/vc709/ug887-vc709-eval-board-v7-fpga.pdf.Search in Google Scholar
AMD (2019). Virtex-7 Family Overview, AMD, San Jose, http://www.xilinx.com/support/documentation/data_sheets/ds183_Virtex_7_Data_Sheet.pdf.Search in Google Scholar
Anceau, F. (1986). The Architecture of Microprocessors, Addison-Wesley, Workingham.Search in Google Scholar
Baranov, S. (1994). Logic Synthesis of Control Automata, Kluwer Academic Publishers, Dordrecht.Search in Google Scholar
Baranov, S. (2008). Logic and System Design of Digital Systems, TUT Press, Tallinn.Search in Google Scholar
Barkalov, A.A., Titarenko, L. and Mielcarek, K. (2022). Reducing LUT count for Mealy FSMs with transformation of states, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41(5): 1400–1411.Search in Google Scholar
Barkalov, A.A. and Barkalov Jr., A.A. (2005). Design of Mealy finite-state machines with the transformation of object codes, International Journal of Applied Mathematics and Computer Science 15(1): 151–158.Search in Google Scholar
Barkalov, A., Titarenko, L. and Krzywicki, K. (2021). Structural decomposition in FSM design: Roots, evolution, current state—A review, Electronics 10(10): 44.Search in Google Scholar
Barkalov, A., Titarenko, L., Krzywicki, K. and Saburova, S. (2020a). Improving the characteristics of multi-level LUT-based Mealy FSMs, Electronics 9(11): 34.Search in Google Scholar
Barkalov, A., Titarenko, L., Mielcarek, K. and Chmielewski, S. (2020b). Logic Synthesis for FPGA-Based Control Units—Structural Decomposition in Logic Design, Springer, Berlin, DOI: 10.1007/978-3-030-38295-7.Search in Google Scholar
Barkalov, O., Titarenko, L. and Mielcarek, K. (2018). Hardware reduction for LUT-based Mealy FSMs, International Journal of Applied Mathematics and Computer Science 28(3): 595–607, DOI: 10.2478/amcs-2018-0046.Search in Google Scholar
Barkalov, O., Titarenko, L. and Mielcarek, K. (2020c). Improving characteristics of LUT-based Mealy FSMs, International Journal of Applied Mathematics and Computer Science 30(4): 745–759, DOI: 10.34768/amcs-2020-0055.Search in Google Scholar
Borowczak, M. and Vemuri, R. (2013). Secure controllers: Requirements of S*FSM, Midwest Symposium on Circuits and Systems, Washington DC, USA, pp. 553–557.Search in Google Scholar
Brayton, R. and Mishchenko, A. (2010). ABC: An academic industrial-strength verification tool, in T. Touili et al. (Eds), Computer Aided Verification, Springer, Berlin/Heidelberg, pp. 24–40.Search in Google Scholar
Chapman, K. (2014). Multiplexer design techniques for datapath performance with minimized routing resources, Xilinx All Programmable, https://docs.xilinx.com/v/u/en-US/xapp522-mux-design-techniques.Search in Google Scholar
Feng, W., Greene, J. and Mishchenko, A. (2018). Improving FPGA performance with a S44 LUT structure, Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, USA, pp. 61–66.Search in Google Scholar
Gajski, D.D., Abdi, S., Gerstlauer, A. and Schirner, G. (2009). Embedded System Design: Modeling, Synthesis and Verification, 1st Edn, Springer, Berlin.Search in Google Scholar
Intel (2023). Corporate website, http://www.intel.com, (formerly Altera).Search in Google Scholar
Islam, M.M., Hossain, M., Shahjalal, M., Hasan, M.K. and Jang, Y.M. (2020). Area-time efficient hardware implementation of modular multiplication for elliptic curve cryptography, IEEE Access 8: 73898–73906.Search in Google Scholar
Klimovich, A.S. and Solov’ev, V.V. (2012). Minimization of Mealy finite-state machines by internal states gluing, International Journal of Computer and Systems Sciences 51(2): 244–255, DOI: 10.1134/S1064230712010091.Search in Google Scholar
Krishnamoorthy, S. and Tessier, R. (2003). Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(5): 545–559.Search in Google Scholar
Kubica, M. and Kania, D. (2017). Area-oriented technology mapping for LUT-based logic blocks, International Journal of Applied Mathematics and Computer Science 27(1): 207–222, DOI: 10.1515/amcs-2017-0015.Search in Google Scholar
Kubica, M., Kania, D. and Kulisz, J. (2019). A technology mapping of FSMs based on a graph of excitations and outputs, IEEE Access 7: 16123–16131.Search in Google Scholar
Kubica, M., Opara, A. and Kania, D. (2021). Technology Mapping for LUT-Based FPGA, Springer, Cham.Search in Google Scholar
LGSynth93 (1993). Benchmark suite, https://ddd.fit.cvut.cz/www/prj/Benchmarks/.Search in Google Scholar
Ling, A., Singh, D. and Brown, S. (2005). FPGA technology mapping: A study of optimality, Proceedings of the 42nd Annual Design Automation Conference, Anaheim, USA, pp. 427–432.Search in Google Scholar
Machado, L. and Cortadella, J. (2020). Support-reducing decomposition for FPGA mapping, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39(1): 213–224.Search in Google Scholar
Marwedel, P. (2018). Embedded System Design: Embedded Systems Foundations of Cyber-Physical Systems, and the Internet of Things, 3rd Edn, Springer, Cham.Search in Google Scholar
Micheli, G.D. (1994). Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York.Search in Google Scholar
Microchip (2023). Corporate website, http://www.microchip.com, (formerly Atmel).Search in Google Scholar
Milik, A. (2016). On hardware synthesis and implementation of PLC programs in FPGAs, Microprocors and Microsystems 44(C): 2–16, DOI: 10.1016/j.micpro.2016.02.003.Search in Google Scholar
Minns, P. and Elliot, I. (2008). FSM-based Digital Design Using Verilog HDL, Wiley, Chichester.Search in Google Scholar
Ruiz-Rosero, J., Ramirez-Gonzalez, G. and Khanna, R. (2019). Field programmable gate array applications—A scientometric review, Computation 7(4): 63.Search in Google Scholar
Scholl, C. (2001). Functional Decomposition with Application to FPGA Synthesis, Kluwer Academic Publishers, Boston.Search in Google Scholar
Senhadji-Navaro, R. and Garcia-Vargas, I. (2015). High-speed and area-efficient reconfigurable multiplexer bank for RAM-based finite state machine implementations, Journal of Circuits, Systems and Computers 24(07): 1550101.Search in Google Scholar
Senhadji-Navarro, R. and Garcia-Vargas, I. (2018). High-performance architecture for binary-tree-based finite state machines, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37(4): 796–805.Search in Google Scholar
Sentowich, E., Singh, K., Lavango, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P., Bryton, R. and Sangiovanni-Vincentelli, A. (1992a). SIS: A system for sequential circuit synthesis, Technical report, University of California, Berkeley.Search in Google Scholar
Sentowich, E., Singh, K., Lavango, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Savoj, H., Stephan, P., Bryton, R. and Sangiovanni-Vincentelli, A. (1992b). SIS: A system for sequential circuit synthesis, Proceedings of the International Conference of Computer Design (ICCD’92), Berkeley, USA, pp. 328–333.Search in Google Scholar
Skliarova, I., Sklyarov, V. and Sudnitson, A. (2012). Design of FPGA-Based Circuits Using Hierarchical Finite State Machines, TUT Press, Tallinn.Search in Google Scholar
Sklyarov, V., Skliarova, I., Barkalov, A. and Titarenko, L. (2014). Synthesis and Optimization of FPGA-Based Systems, Springer, Cham.Search in Google Scholar
Solovjev, V. and Czyzy, M. (1999). Refined CPLD macrocells architecture for effective FSM implementation, Proceedings of the 25th EUROMICRO Conference, Milan, Italy, Vol. 1, pp. 102–109.Search in Google Scholar
Sutter, G., Todorovich, E., López-Buedo, S. and Boemo, E. (2002). Low-power FSMs in FPGA: Encoding alternatives, in B. Hochet et al. (Eds), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, Berlin/Heidelberg, pp. 363–370.Search in Google Scholar
Tiwari, A. and Tomko, K. (2004). Saving power by mapping finite-state machines into embedded memory blocks in FPGAs, Design, Automation and Test in Europe Conference and Exhibition, Paris, France, Vol. 2, pp. 916–921.Search in Google Scholar
Trimberger, S. (2015). Three ages of FPGA: A retrospective on the first thirty years of FPGA technology, IEEE Proceedings 103(3): 318–331.Search in Google Scholar
Vivado (2023). Design tools documentation, https://www.xilinx.com/products/design-tools/vivado.html.Search in Google Scholar
Wolf, W. (2004). FPGA-Based System Design, Prentice Hall PTR, Upper Saddle River.Search in Google Scholar
Zgheib, G. and Ouaiss, I. (2015). Enhanced technology mapping for FPGAs with exploration of cell configurations, Journal of Circuits, Systems and Computers 24(3): 1550039.Search in Google Scholar
