1. bookVolume 32 (2022): Issue 3 (September 2022)
    Recent Advances in Modelling, Analysis and Implementation of Cyber-Physical Systems (Special section, pp. 345-413), Remigiusz Wiśniewski, Luis Gomes and Shaohua Wan (Eds.)
Journal Details
License
Format
Journal
eISSN
2083-8492
First Published
05 Apr 2007
Publication timeframe
4 times per year
Languages
English
Open Access

Improving the LUT Count for Mealy FSMS with Transformation of Output Collections

Published Online: 08 Oct 2022
Volume & Issue: Volume 32 (2022) - Issue 3 (September 2022) - Recent Advances in Modelling, Analysis and Implementation of Cyber-Physical Systems (Special section, pp. 345-413), Remigiusz Wiśniewski, Luis Gomes and Shaohua Wan (Eds.)
Page range: 479 - 494
Received: 09 Dec 2021
Accepted: 23 Mar 2022
Journal Details
License
Format
Journal
eISSN
2083-8492
First Published
05 Apr 2007
Publication timeframe
4 times per year
Languages
English

Achasova, S. (1987). Synthesis Algorithms for Automata with PLAs,M: Soviet Radio, Moscow. Search in Google Scholar

Altera (2021). Corporate website, http://www.altera.com/, (currently: Intel Corporation, https://www.intel.com/content/www/us/en/products/programmable.html. Search in Google Scholar

Amano, H. (2018). Principles and Structures of FPGAs, Springer Singapore, Singapore.10.1007/978-981-13-0824-6 Search in Google Scholar

Atmel (2021). Corporate website, http://www.atmel.com/, (currently: Microchip Technology, https://www.microchip.com/. Search in Google Scholar

Baranov, S. (1994). Logic Synthesis of Control Automata, Kluwer Academic Publishers, Boston.10.1007/978-1-4615-2692-6 Search in Google Scholar

Baranov, S. (2008). Logic and System Design of Digital Systems, TUT Press, Tallinn. Search in Google Scholar

Barkalov, A. A. and Barkalov Jr., A. A. (2005). Design of Mealy finite-state machines with the transformation of object codes, International Journal of Applied Mathematics and Computer Science 15(1): 151–158. Search in Google Scholar

Barkalov, A., Titarenko, L. and Krzywicki, K. (2021b). Structural decomposition in FSM design: Roots, evolution, current state—A review, Electronics 10(10): 1–44.10.3390/electronics10101174 Search in Google Scholar

Barkalov, A., Titarenko, L., Krzywicki, K. and Saburova, S. (2020a). Improving the characteristics of multi-level LUT-based Mealy FSMs, Electronics 9(11): 1–34.10.3390/electronics9111859 Search in Google Scholar

Barkalov, A., Titarenko, L., Mazurkiewicz, M. and Krzywicki, K. (2021a). Improving LUT count of FPGA-based sequential blocks, Bulletin of the Polish Academy of Sciences: Technical Sciences 69(2): 1–12, DOI: 10.24425/bpasts.2021.136728. Search in Google Scholar

Barkalov, A., Titarenko, L. and Mielcarek, K. (2018). Hardware reduction for LUT-based Mealy FSMs, International Journal of Applied Mathematics and Computer Science 28(3): 595–607, DOI: 10.2478/amcs-2018-0046.10.2478/amcs-2018-0046 Search in Google Scholar

Barkalov, A., Titarenko, L. and Mielcarek, K. (2020b). Improving characteristics of LUT-based Mealy FSMs, International Journal of Applied Mathematics and Computer Science 30(4): 745–759, DOI: 10.34768/amcs-2020-0055. Search in Google Scholar

Barkalov, A., Titarenko, L., Mielcarek, K. and Chmielewski, S. (2020c). Logic Synthesis for FPGA-Based Control Units -Structural Decomposition in Logic Design, Lecture Notes in Electrical Engineering, Vol. 636, Springer, Berlin, DOI: 10.1007/978-3-030-38295-7.10.1007/978-3-030-38295-7 Search in Google Scholar

Borowczak, M. and Vemuri, R. (2013). Secure controllers: Requirements of S*FSM, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, USA, pp. 553–557, DOI: 10.1109/MWSCAS.2013.6674708.10.1109/MWSCAS.2013.6674708 Search in Google Scholar

Brayton, R. and Mishchenko, A. (2010). ABC: An academic industrial-strength verification tool, in T. Touili et al. (Eds), Computer Aided Verification, Springer, Berlin/Heidelberg, pp. 24–40.10.1007/978-3-642-14295-6_5 Search in Google Scholar

Chapman, K. (2014). Multiplexer design techniques for datapath performance with minimized routing resources, Xilinx Application Note 522 (v1.2), https://www.xilinx.com/support/documentation/application_notes/xapp522-mux-design-techniques.pdf. Search in Google Scholar

Das, N. and Panchanathan, A. (2018). FPGA implementation of reconfigurable finite state machine with input multiplexing architecture using Hungarian method, International Journal of Reconfigurable Computing 2018, Article ID: 6831901, DOI: 10.1155/2018/6831901.10.1155/2018/6831901 Search in Google Scholar

Feng, W., Greene, J. and Mishchenko, A. (2018). Improving FPGA performance with a S44 LUT structure, FPGA’18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, USA, pp. 61–66, DOI: 10.1145/3174243.3174272.10.1145/3174243.3174272 Search in Google Scholar

Islam, M.M., Hossain, M.S., Shahjalal, M., Hasan, M.K. and Jang, Y.M. (2020). Area-time efficient hardware implementation of modular multiplication for elliptic curve cryptography, IEEE Access 8: 73898–73906.10.1109/ACCESS.2020.2988379 Search in Google Scholar

Kubica, M. and Kania, D. (2017). Area-oriented technology mapping for LUT-based logic blocks, International Journal of Applied Mathematics and Computer Science 27(1): 207–222, DOI: 10.1515/amcs-2017-0015.10.1515/amcs-2017-0015 Search in Google Scholar

Kubica, M., Kania, D. and Kulisz, J. (2019). A technology mapping of FSMs based on a graph of excitations and outputs, IEEE Access 7: 16123–161131, DOI: 10.1109/ACCESS.2019.2895206.10.1109/ACCESS.2019.2895206 Search in Google Scholar

Kubica, M., Opara, A. and Kania, D. (2017). Logic synthesis for FPGAs based on cutting of BDD, Microprocessors and Microsystems 52(C): 173–187, DOI: 10.1016/j.micpro.2017.06.010.10.1016/j.micpro.2017.06.010 Search in Google Scholar

Kubica, M., Opara, A. and Kania, D. (2021). Technology Mapping for LUT-Based FPGA, Lecture Notes in Electrical Engineering, Vol. 13, Springer International Publishing, Cham. Search in Google Scholar

LGSynth93 (1993). Benchmark suite, https://people.engr.ncsu.edu/brglez/CBL/benchmarks/LGSynth93/LGSynth93.tar. Search in Google Scholar

Machado, L. and Cortadella, J. (2020). Support-reducing decomposition for FPGA mapping, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39(1): 213–224, DOI: 10.1109/TCAD.2018.2878187.10.1109/TCAD.2018.2878187 Search in Google Scholar

Marwedel, P. (2018). Embedded System Design: Embedded Systems Foundations of Cyber-Physical Systems, and the Internet of Things, 3rd Edn, Springer International Publishing, Cham, DOI: 10.1007/978-3-319-56045-8.10.1007/978-3-319-56045-8 Search in Google Scholar

Maxfield, C. (2008). FPGAs: Instant Access, Newnes, Burlington. Search in Google Scholar

Micheli, G.D. (1994). Synthesis and Optimization of Digital Circuits, McGraw-Hill, Berkshire. Search in Google Scholar

Minns, P. and Elliot, I. (2008). FSM-based Digital Design Using Verilog HDL, John Wiley and Sons, Chichester.10.1002/9780470987629 Search in Google Scholar

Ruiz-Rosero, J., Ramirez-Gonzalez, G. and Khanna, R. (2019). Field programmable gate array applications—A scientometric review, Computation 7(4): 63, DOI: 10.3390/computation7040063.10.3390/computation7040063 Search in Google Scholar

Sasao, T. and Mishchenko, A. (2009). LUTMIN: FPGA logic synthesis with MUX-based and cascade realizations, International Workshop on Logic Synthesis, Berkeley, USA, pp. 310–316. Search in Google Scholar

Scholl, C. (2001). Functional Decomposition with Application to FPGA Synthesis, Kluwer, Boston.10.1007/978-1-4757-3393-8 Search in Google Scholar

Senhadji-Navaro, R. and Garcia-Vargas, I. (2015). High-speed and area-efficient reconfigurable multiplexer bank for RAM-based finite state machine implementations, Journal of Circuits, Systems and Computers 24(07): 1550101:1–1550101:15, DOI: 10.1142/S0218126615501017.10.1142/S0218126615501017 Search in Google Scholar

Skliarova, I., Sklyarov, V. and Sudnitson, A. (2012). Design of FPGA-based Circuits using Hierarchical Finite State Machines, TUT Press, Tallinn.10.1109/IranianCEE.2013.6599683 Search in Google Scholar

Sklyarov, V. (2000). Synthesis and implementation of RAM-based finite state machines in FPGAs, in R.W. Hartenstein and H. Grünbacher (Eds), Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, Springer, Berlin/Heidelberg, pp. 718–727.10.1007/3-540-44614-1_76 Search in Google Scholar

Sklyarov, V., Skliarova, I., Barkalov, A. and Titarenko, L. (2014). Synthesis and Optimization of FPGA-Based Systems, Lecture Notes in Electrical Engineering, Vol. 294, Springer-Verlag, Berlin. Search in Google Scholar

Solovjev, V. and Czyzy, M. (1999). Refined CPLD macrocells architecture for effective FSM implementation, Proceedings of the 25th EUROMICRO Conference, Milan, Italy, Vol. 1, pp. 102–109. Search in Google Scholar

Sutter, G., Todorovich, E., López-Buedo, S. and Boemo, E. (2002). Low-power FSMs in FPGA: Encoding alternatives, in B. Hochet et al. (Eds), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, Berlin/Heidelberg, pp. 363–370.10.1007/3-540-45716-X_36 Search in Google Scholar

Tiwari, A. and Tomko, K. (2004). Saving power by mapping finite-state machines into embedded memory blocks in FPGAs, Proceedings of the conference on Design, Automation and Test in Europe, Paris, France, Vol. 2, pp. 916–921. Search in Google Scholar

Trimberg, S. (2015). Three ages of FPGA: A retrospective on the first thirty years of FPGA Technology, IEEE Proceedings 103(3): 318–331.10.1109/JPROC.2015.2392104 Search in Google Scholar

Vivado (2021). CAD tools website, https://www.xilinx.com/products/design-tools/vivado.html. Search in Google Scholar

Wolf, W. (2004). FPGA-Based System Design, Prentice Hall PTR, Upper Saddle River. Search in Google Scholar

Xilinx (2020). VC709 Evaluation Board for the Virtex-7 FPGA, https://www.xilinx.com/support/documentation/boards_and_kits/vc709/ug887-vc709-eval-board-v7-fpga.pdf. Search in Google Scholar

Xilinx (2021). Corporate website, http://www.xilinx.com/. Search in Google Scholar

Recommended articles from Trend MD

Plan your remote conference with Sciendo