Impact of lanthanum doped zirconium oxide (LaZrO₂) gate dielectric material on FinFET inverter

Recently, several miniature devices have developed for low power and high-performance application circuits. It has inspected that fin-typed field effect transistor (FinFET) device shows a substantial reduction in short channel effects (SCEs) as well as leakage current, better switching rate, and consumes less power in comparison to other devices (Gargini, 2020; Colinge, 2008; Sachid and Chenming, 2012). For satisfying the need for the latest portable appliances such as mobile phones, microprocessors, cache memories in computers, the FinFET device has been considered as an appropriate solution. Most of the semiconductors industries such as Samsung, Intel, TSMC, and global foundries are utilizing FinFET devices in their latest processors (Businesswire, 2017). The authors have designed the FinFET-based accumulator to store temporary data bits in the memory (Sathya et al., 2017). FET-based biosensors have also been developed with the help of evolutionary algorithms for biomedical applications. Thus, this device includes additional features viz. high switching speed, low leakage, and small size, making it a prominent substitute in every application field (Sharma and Kumar, 2019a, 2019b; Pindoo and Sinha, 2020; Rathee et al., 2019). Higher leakage current and subthreshold slope in GAA-FET make it unsuitable for low power applications. The device design with novel materials remains the target research area for the IC design engineers. In sub-22 nm technology, the direct tunneling gate leakage current has reduced with novel high-k gate dielectric materials like Al₂O₃ (k = 9), ZrO₂ (25), HfO₂ (25), TiO₂ (80), Y₂O₃ (15), Ta₂O₅ (22), LaZrO₂ (40), and CeO₂ (23-26). It has observed that for suitable future scaling, a dielectric with k over 40 is preferred, and lanthanum doped zirconium oxide (LaZrO₂) has been considered as the promising high-k gate dielectric material for sub-22 nm node FinFET devices (Gaskell et al., 2007; Zhao et al., 2012; Liu et al., 2019; Cheng et al., 1999; Wikipedia 14nm process, 2020).

In this work, the impact on the performance of 14 nm SOI FinFET has been analyzed with conventional SiO₂ and high-k gate dielectric materials, LaZrO₂. Further, n-FinFET (N channel FinFET) and p-FinFET (P channel FinFET) devices of the same dimensions have been devised using common gate material (workfunction = 4.6 eV) and LaZrO2 (k = 40) as gate oxide material (Zhao et al., 2011). The inverter circuit designed with these devices explained its suitability in circuit applications. The proposed circuit’s performance has been analyzed by calculating the noise margin of a single fin configuration. The noise margin (0.375 V) of the simulated inverter circuit has revealed 17% progress as compared to results claimed for the nanowire field-effect transistor (0.32 V) based inverter circuits (Nayak et al., 2014).

The paper has been organized as: the second section explained the design and simulation methodology of the device. Next, the third section discussed the results of the designed FinFET device and its comparison with existing work. Subsequent the fourth section illustrated the performance of FinFET-based inverter. The impact of temperature and voltage variations on the circuit’s noise margin has also been described in the same section. In the last section, the conclusion and future scope of work have been discussed.

The 3D structures of n-FinFET with different perspectives have shown in Figures 1 and 2. Table 1 illustrates the device design considerations for n-FinFET and p-FinFET. The novel material LaZrO₂ (k = 40) high-k gate dielectric has been used for 14 nm FinFETs (Zhao, Zhao, Werner, Taylor and Chalker, 2012; Cheng et al., 1999; Zhao, Zhao, Tao, Werner, Taylor and Chalker, 2012; Kaur et al., 2019). Table 2 describes the important technology computer-aided design (TCAD) device parameters of 14 nm processes for an inverter model, according to International Technology Roadmap for Semiconductors (ITRS) (Wikipedia 14nm process, 2020; Zhao et al., 2011, 2012; Nayak et al., 2014; Kaur et al., 2019; Genius User Guide, 2009; Ana and Din, 2011). The simulator’s validity has been examined by matching its results with published experimental data in the TCAD environment at 300 K as shown in Fig. 2 (de Andrade et al., 2011). Therefore, it shows that this paper’s models and parameters are valid (Genius User Guide, 2009). The proposed devices have simulated using the following models:

Drift diffusion model (DDM), which solves a particular set of Poisson equations, as mentioned in the following equation: (1) ∇ . ε ∇ ψ = − q ( p − n + N D + − N A − ) , (1)where ψ ψ is the electrostatic potential of the vacuum level; n and p represents the electron and hole concentration; N D + and N A − represents the ionized doping concentration; q is an electron charge. The lattice temperature is kept uniform throughout the drift diffusion model.

Figure 1:

Figure 2:

Figure 3:

Figure 4:

The set of performance parameters evaluated for the designed structure are drain current at highest value of gate voltage (I_ON); drain current at lowest value of gate voltage (I_OFF); I_ON/I_OFF current ratio; subthreshold swing (SS = ∂V_g/∂log10I_d); drain-induced barrier lowering (DIBL); threshold voltage (V_t); transconductance (g_m= ∂I_d/∂V_g); transconductance generation factor (TGF = g_m/I_d); output transconductance (g_d = ∂I_d/∂V_d); intrinsic gain (A_V = 20 × log10(g_m/g_d), and early voltage (V_EA = I_d/g_d). These parameters have been computed with gate voltage (V_g) variation of 0 to 0.75 V and drain voltage (V_d) 50 mV and 0.75 V as the boundary condition. The difference of gate voltage corresponding to both 20 mV and 0.75 V drain voltage at drain current (I_DIBL) of 4 × 10⁻⁷ A evaluates DIBL with the formulae stated in the following equation: (5) I D I B L = W e f f L g × 10 − 7 A , (5)where W_eff indicates channel effective width which has measured from the following equation: (6) W e f f = 2 H F i n + W F i n .

The constant current method has been used to extract the value of threshold voltage (Siebel et al., 2012).

The transfer characteristics of n-FinFET in log and a linear scale for L_g=14 nm, V_g=0 to 0.75 V, and V_d=0.75 V has outlined in Figure 5. It has been observed that extracted I_ON (4.95×10⁻⁵) and I_OFF (3.61×10⁻¹⁴) showed thrice enhancement and 10⁻⁴ factor reduction as compared to the results claimed for the same technology (Lee, 2016; Nirmal et al., 2012). The impact on the performance of the n-FinFET device due to conventional SiO₂ and novel high-k gate dielectric materials, LaZrO₂ have been justified in Table 3. The device optimizations of n-FinFET and p-FinFET have done using work function engineering to obtain the improved results for an inverter circuit.

Figure 5:

Performance optimization of n-FinFET and p-FinFET devices using work function engineering

The design optimization of n-FinFET and p-FinFET devices have been done with superior lanthanum doped zirconium oxide gate material. The perfect V-curve for n-FinFET and p-FinFET have established for saturation (at 0.75 V) and linear (at 50 mV) operation as congregated in Figures 6 and 7. The similar performances for both devices are realized due to work function engineering using a mid-gap band of 4.6 eV and are outlined in Table 4 (Eng et al., 2018; Knoblinger et al., 2008). It has been reported that enhancement in value of work function and high-k gate dielectric material improves the current ratio and lessens device’s SS (Kaur et al., 2020a, b). Figure 7 signifies the output characteristic curve for both devices at the supply voltage of 0.5, 0.6, 0.75, 0.8, and 0.85 V.

Table 4.

Performance analysis of FinFET devices.

	n-FinFET		p-FinFET
Metrics	Lin (Vd = 50 mV)	Sat (Vd = 0.75 V)	Lin (Vd = 50 mV)	Sat (Vd = 0.75 V)
ION (A)	1.37 × 10−5	4.95 × 10−5	1.81 × 10−5	4.54 × 10−5
IOFF(A)	2.64 × 10−14	3.61 × 10−14	2.69 × 10−14	3.98 × 10−14
ION/IOFF	0.51 × 109	1.37 × 109	0.67 × 109	1.14 × 109
SS (mV/dec)	59.9	60.3	59.9	60.9
Vt (V)	0.261	0.253	0.262	0.253
gm (S)	5.88 × 10−5	2.42 × 10−4	4.71 × 10−5	2.33 × 10−4
TGF (V−1)	24.68	24.55	24.65	24.37
DIBL (mV/V)	10.1	12.3

Figure 6:

Figure 7:

An inverter circuit has devised in shorted gate (SG) mode configuration by utilizing optimized n-FinFET and p-FinFET devices. The circuit dimensions have shown in Table 2.

The SG mode configuration has preferred due to the advantage of improved drive strength and gate-controlled channel. The schematic layout of the designed FinFET-based inverter and structural dimensions has presented in Figure 8. Further, noise margins (NM) have been measured for analyzing the performance of the circuit.

Figure 8:

It has defined as the maximum allowable spurious signal accepted by a device without affecting the circuit (VLSI System Design, VLSI Basics, 2019; Yeh et al., 2018). The butterfly curve (VTC) of the FinFET-based inverter has delineated in Figure 9 for two different voltages. It inferred that the devised inverter circuit performs satisfactory at a low supply voltage of 0.4 V. The estimated high noise margin (NMH) and low noise margins (NML) at a supply voltage of 0.8 and 0.4 V are 0.375, 0.375 V and 0.195, 0.12 V, respectively. The NM of the simulated circuit is improved by 17% (0.375 V) as compared to results derived by authors for nanowire field-effect transistor-based inverter (0.32 V) (Nayak et al., 2014). The determined static power consumption for a circuit is 3×10⁻¹⁴W (Li et al., 2007).

Figure 9:

The dependence of noise margin on temperature (273, 300, 398 K) and voltage (0.4, 0.8, 1.2 V) variations have been analyzed for LaZrO₂ gate dielectric and delineated in Table 5. It perceived that the increased operating voltage and reduced temperature induces improvement in the noise margin. The degraded noise margin has been observed for lower voltage and higher temperatures (Chakraborty et al., 2013; Bortolon, 2018; Pattanaik et al., 2012).

The impact of compound high-k gate dielectric LaZrO₂ on the device’s performance has studied using Cogenda TCAD with the drift-diffusion transport framework. The incorporation of high-k dielectric in SOI FinFET devices improves its scalability, reduces chip area, and enhances the storage capacity, making it suitable for high-speed applications and memories. It has been found that the proposed device demonstrates superior SCEs immunity by giving a 10% reduction in SS and 76% decrement in DIBL for LaZrO₂ gate oxide compared to SiO₂ gate oxide. The I_ON/I_OFF has improved by two orders of magnitude compared to results claimed in previous generations of MOSFET devices (Lee, 2016). The significant improvements for analog parameters viz. g_m (5.88×10⁻⁵ S), V_EA (10.7 V), and A_V (183 dB) in the linear region have also been observed, which evaluate its suitability in circuit applications. Further, optimized n-FinFET and p-FinFET devices have been devised for implementing an inverter. A remarkable advancement in NM (0.375 V) of an inverter circuit has been realized compared to acceptable NMs mentioned in the research paper (Nayak et al., 2014). Although the proposed device and its inverter circuit present progress, therefore SRAM implementation can be done in the future.