<abstract xmlns="http://www.w3.org/1999/xhtml"><p>This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm<sup>2</sup>, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.</p></abstract>

This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Department of Electrical and Electronics Engineering

Abant Izzet Baysal University, Golkoy Campus

Department of Electronics and Communications Engineering

Journal of Electrical Engineering

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

{"article-title":"A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology"}

This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels...

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Published Online: Jan 19, 2018

Page range: 415 - 424

Received: Oct 26, 2017

DOI: https://doi.org/10.1515/jee-2017-0076

Keywords
analog-to-digital converters, CMOS ADC, time interleaved ADC, flash ADC

© 2017 Oktay Aytar et al., published by De Gruyter Open

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Published Online: Jan 19, 2018

Page range: 415 - 424

Received: Oct 26, 2017

DOI: https://doi.org/10.1515/jee-2017-0076

Keywordsanalog-to-digital converters, CMOS ADC, time interleaved ADC, flash ADC

© 2017 Oktay Aytar et al., published by De Gruyter Open

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Keywords
analog-to-digital converters, CMOS ADC, time interleaved ADC, flash ADC