Open Access

Security Problems of Scan Design and Accompanying Measures


Cite

[1] MARINISSEN, E. J. (moderator) : Security vs Test Quality: Can We Really Only Have One at a Time?, Proc. of the ITC, Charlotte, 2004, pp. 1411.Search in Google Scholar

[2] KAPUR, R. : Security vs Test Quality: Are they mutually exclusive?, Proc. of the ITC, Charlotte, 2004, pp. 1414.Search in Google Scholar

[3] GOERING, R. : EE Times On Line, Latest News, http://www.us.design-reuse.com/news/news8974.html.Search in Google Scholar

[4] WILLIAMS, M. J. Y.-ANGEL, J. B. : Enhancing Testability of Large Scale Integrated Circuits via Test Points and Additional Logic, IEEE Trans. Comput. C-22 No. 1 (1973), 46-60.10.1109/T-C.1973.223600Search in Google Scholar

[5] EICHELBERGER, E. B.-WILLIAMS, T. W. : A Logic Design Structure for LSI Testability, Proc. 14th Des. Autom. Conf., New Orleans, 1977, pp. 462-468.Search in Google Scholar

[6] IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE Std1149.1-2001, Institute of Electrical and Electronics Engineers, 14-Jun-2001.Search in Google Scholar

[7] BLEEKER, H.-VAN DEN EIJUDEN, P.-DE JONG, F. : Boundary-Scan Test, A Practical Approach, Kluwer Acad. Publ, 1993.10.1007/978-1-4615-3132-6Search in Google Scholar

[8] PARKER, K. P. : The Boundary-Scan Handbook, Third edi- tion, Kluwer Acad. Publ., 2003.10.1007/978-1-4615-0367-5Search in Google Scholar

[9] NOVAK, F.-BIASIZZO, A. : Security Extension for IEEE Std 1149.1, Journal of Electronic Testing, Theory and Practice 22 No. 3 (June 2006), 301-303.10.1007/s10836-006-7720-xSearch in Google Scholar

[9] EICHELBERGER, E. B.-LINDBLOOM, E.-WAICUKAUSKI, J. A.-WILLIAMS, T. W. : Structured Logic Testing, Prentice-Hall, 1991.Search in Google Scholar

[10] IEEE Standard for a Mixed-Signal Test Bus. IEEE Std 1149.4-1999. Institute of Electrical and Electronics Engineers, 2000.Search in Google Scholar

[11] IEEE Std 1500-2005. IEEE Standard Testability Method for Embedded Core-based Integrated Circuits. Institute of Electrical and Electronics Engineers, 2005.Search in Google Scholar

[12] YANG, B.-WU, K.-KARRI, R.: Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard,Proc. of the ITC, Charlotte,2004, pp.339-344.Search in Google Scholar

[13] BONNETT, D.: Boundary Scan Goes Underground, Test & Measurement World (Sep 2005), 49-56.Search in Google Scholar

[14] MILLER, A. : Trends in Process Control System Security, IEEE Security & Privacy 3 No. 5 (2005), 57-60.10.1109/MSP.2005.136Search in Google Scholar

[15] US Computer Emergency Readiness Team, Control Systems Cy- ber Security Awareness, http://www.us-cert.gov/readingroom/Control_System_Security.pdf.Search in Google Scholar

[16] ROSENFELD, K.-KARRI, R.: Attacks and Defenses for JTAG, IEEE Design and Test of Computers 27 No. 1 (2010), 36-47.10.1109/MDT.2010.9Search in Google Scholar

[17] CLARK, C. J.: Anti-Tamper JTAG TAP Design Enables DRM to JTAG Registers and P1687 On-Chip Instruments, Proc. HOST 2010, Anaheim, CA, USA, June 2010, pp. 19-24.10.1109/HST.2010.5513119Search in Google Scholar

eISSN:
1339-309X
Language:
English
Publication timeframe:
6 times per year
Journal Subjects:
Engineering, Introductions and Overviews, other