1. bookTom 12 (2019): Zeszyt 1 (September 2019)
Informacje o czasopiśmie
License
Format
Czasopismo
eISSN
2343-8908
Pierwsze wydanie
30 Sep 2018
Częstotliwość wydawania
2 razy w roku
Języki
Angielski
Otwarty dostęp

Characterization of Novel 8T SRAM with Low Leakage and Optimized Area

Data publikacji: 11 Oct 2019
Tom & Zeszyt: Tom 12 (2019) - Zeszyt 1 (September 2019)
Zakres stron: 29 - 36
Informacje o czasopiśmie
License
Format
Czasopismo
eISSN
2343-8908
Pierwsze wydanie
30 Sep 2018
Częstotliwość wydawania
2 razy w roku
Języki
Angielski

[1] S. Robert, Technological innovation in the semiconductor industry: a case study of the International Technology Roadmap for Semiconductors (ITRS). Diss. George Mason University, 2004.Search in Google Scholar

[2] A. Paridhi, and S. Dasgupta, “A Comparative Study of 6T, 8T and 9T Decanano SRAM cell.” Industrial Electronics & Applications, 2009. ISIEA 2009. IEEE Symposium on. Vol. 2. IEEE, 2009.Search in Google Scholar

[3] A. Asen, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva. “Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs.” IEEE transactions on electron devices 50, no. 9 (2003): 1837-1852.10.1109/TED.2003.815862Search in Google Scholar

[4] M. Tomohisa, J. Okumtura, and A. Toriumi. “Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET’s.” IEEE Transactions on Electron Devices 41, no. 11 (1994): 2216-2221.10.1109/16.333844Search in Google Scholar

[5] G. F. Cardinale, et al. “Demonstration of pattern transfer into sub-100 nm polysilicon line/space features patterned with extreme ultraviolet lithography.” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 17.6 (1999): 2970-2974.10.1116/1.590936Otwórz DOISearch in Google Scholar

[6] J. Singh, D. K. Pradhan, S. Hollis, &, S. P. Mohanty (2008), “A single ended 6T SRAM cell design for ultra-low-voltage applications”. IEICE Electronics Express, 5(18), 750-755.10.1587/elex.5.750Search in Google Scholar

[7] H. Mizuno, & T. Nagano, (1996). “Driving source-line cell architecture for sub-1-V high-speed low-power applications”. IEICE transactions on electronics, 79(7), 963-968.Search in Google Scholar

[8] Z. Bo, et al. “A Sub-200mV 6T SRAM in 0.13um CMOS in Solid-State Circuits Conference,” 2007. ISSCC 2007. Digest of Technical Papers. IEEE International. 2007.Search in Google Scholar

[9] A. Touqeer, B. Cheng, and D.R. Cumming. “Variability resilient low-power 7T-SRAM design for nano-scaled technologies.” Quality Electronic Design (ISQED), 2010 11th International Symposium on. IEEE, 2010.Search in Google Scholar

[10] K. F. Sharif, R. Islam, M. Haque. M. A. Keka, & S. N. Biswas, (2017, February). “7T SRAM based memory cell”. In Innovative Mechanisms for Industry Applications (ICIMIA), 2017 International Conference on (pp. 191-194). IEEE.10.1109/ICIMIA.2017.7975599Search in Google Scholar

[11] M. Moghaddam, M. H. Moaiyeri, & M. Eshghi, (2015, May). “Ultra low-power 7T SRAM cell design based on CMOS”. In Electrical Engineering (ICEE), 2015 23rd Iranian Conference on (pp. 1357-1361). IEEE.10.1109/IranianCEE.2015.7146428Search in Google Scholar

[12] P. Macken, M. Degrauwe, M. Van Paemel, &, H. Oguey (1990, February). “A voltage reduction technique for digital systems”. In Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC, 1990 IEEE International (pp. 238-239). IEEE.10.1109/ISSCC.1990.110213Search in Google Scholar

[13] R. Gupta, &, S, Dasgupta. (2017). “Process Corners Analysis of Data Retention Voltage (DRV) for 6T, 8T, and 10T SRAM Cells at 45 nm”. IETE Journal of Research, 1-6.Search in Google Scholar

[14] Anh-Tuan, Do, et al. “An 8T differential SRAM with improved noise margin for bit-interleaving in 65 nm CMOS.” IEEE Transactions on Circuits and Systems I: Regular Papers 58.6 (2011): 1252-1263.10.1109/TCSI.2010.2103154Search in Google Scholar

[15] M. Yabuuchi, K. Nii, Y Tsukamoto, S. Ohbayashi, Y. Nakase, & H. Shinohara, (2009, June). “A 45nm 0.6 V cross-point 8T SRAM with negative biased read/write assist.” In VLSI Circuits, 2009 Symposium on (pp. 158-159). IEEE.Search in Google Scholar

[16] http://ptm.asu.eduSearch in Google Scholar

[17] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, “Digital Integrated Circuits: A Design Perspective”, 2nd ed. New Delhi, India: Prentice-Hall, 2005.Search in Google Scholar

[18] P. Raikwal, V. Neema, & A. Verma, (2017, April). “High speed 8T SRAM cell design with improved read stability at 180nm technology”. In Electronics, Communication and Aerospace Technology (ICECA), 2017 International conference of (Vol. 2, pp. 563-568). IEEE.10.1109/ICECA.2017.8212727Search in Google Scholar

[19] K. F. Sharif, R. Islam, S. N. Biswas, & V. Groza. (2017, April). “4 Transistor and 2 memristor based memory”. In Computer Applications & Industrial Electronics (ISCAIE), 2017 IEEE Symposium on (pp. 37-40). IEEE.10.1109/ISCAIE.2017.8074946Search in Google Scholar

[20] C. Benton and A. P. Chandrakasan. “Static noise margin variation for sub-threshold SRAM in 65-nm CMOS.” IEEE Journal of solid-state circuits 41.7 (2006): 1673-1679.10.1109/JSSC.2006.873215Search in Google Scholar

[21] K. F. Sharif, R. Islam, M. Haque, S. N. Biswas, V. Groza, & M. Assaf, (2017, February). “Low power nMOS based memory cell”. In Innovative Mechanisms for Industry Applications (ICIMIA), 2017 International Conference on (pp. 186-190). IEEE10.1109/ICIMIA.2017.7975598Search in Google Scholar

[22] K.F. Sharif, R. Islam and S.N. Biswas, “Low Power Novel 10T SRAM with Stabled Optimized Area.” In 2018 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE), pp. 21-24. IEEE, 2018.10.1109/WIECON-ECE.2018.8783036Search in Google Scholar

[23] E. Seevinck, F. List, J. Lohstroh, “Static noise margin analysis of MOS SRAM cells”, IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748-754, Oct. 1987.10.1109/JSSC.1987.1052809Search in Google Scholar

[24] K.F. Sharif, R. Islam and S.N. Biswas, “A New Model of High Speed 7T SRAM Cell”. In 2018 International Conference on Computer, Communication, Chemical, Material and Electronic Engineering (IC4ME2) (pp. 1-4). IEEE. 2018, February10.1109/IC4ME2.2018.8465611Search in Google Scholar

[25] A. Islam, and M. Hasan. “A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell.” Microelectronics Reliability 52.2 (2012): 405-411.10.1016/j.microrel.2011.09.034Search in Google Scholar

[26] C. Binjie, et al. “Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells.” Solid-State Electronics 49.5 (2005): 740-746.10.1016/j.sse.2004.09.005Search in Google Scholar

[27] S. Abhijit, S. Ghosh, and M. Bayoumi. “A novel 90nm 8T SRAM cell with enhanced stability.” Integrated Circuit Design and Technology, 2007. ICICDT’07. IEEE International Conference on. IEEE, 2007.Search in Google Scholar

Polecane artykuły z Trend MD

Zaplanuj zdalną konferencję ze Sciendo